1. Field of the Invention
The invention relates to a high-speed sense current amplifier with a low power consumption for a memory cell.
2. Description of the Related Art
Semiconductor memories are binary data memories in which the individual memory cells SZ are arranged in matrix form and comprise semiconductor components, in particular transistors. In this case, the memory cells SZ are connected to word lines WL and bit lines BL, running perpendicularly thereto. The matrix contains n*m memory cells. The addressing, i.e. the selection of a memory cell SZ or a memory word, is effected by activation of the word lines WL. In this case, the addressing is performed by an address decoder which, given n external address lines, internally generates 2n selection signals for word line and bit line selection. The data information items contained in the memory cells SZ are read out via a sense amplifier.
FIG. 1 schematically shows the construction of a semiconductor memory arrangement. The address decoder D is connected to an address bus AR and decodes the addressing signal present on the address bus AR for the selection of memory cells SZ within the semiconductor memory. The read-out data contained in the memory cells SZ pass via memory signal lines to a multiplexer MUX, which is connected to the sense amplifier on the output side. The sense amplifier amplifies the received memory signal and outputs it to a data bus DR via an output buffer P.
FIG. 2 schematically shows part of a sense current amplifier for the read-out and amplification of the data content contained in a memory cell SZ, according to the prior art.
The memory cell SZ contains a data bit information item, the memory cell SZ being in a logic low state L(low) or a logic high state H(high). The memory cell SZ may be a RAM memory cell or a ROM memory cell. The memory cell SZ is addressed via a word line WL leading away from the decoder D and outputs the data content contained in it via the bit line BL. In this case, a memory signal current IBL flows via the memory signal line or bit line BL to the multiplexer MUX. The memory signal current IBL is zero if the memory cell SZ is in a logic low state L. If the memory cell SZ is in a logic high state H, a predetermined memory signal current IBL flows. The bit line BL has a line capacitance and can be precharged or recharged via a charging circuit comprising e.g. a clocked MOSFET transistor. The multiplexer MUX is controlled in a manner dependent on a selection signal SS1 and through-connects the memory signal line BL to the input E of the sense current amplifier LSV. The sense current amplifier LSV contains a current mirror circuit which is supplied with a supply voltage VDD. On the output side, the current mirror circuit is connected to a node which is connected to the output A of the sense current amplifier LSV according to the prior art. The current mirror circuit amplifies the memory signal current IBL received via the input E with a constant factor K and outputs the amplified current Kxc2x7IBL at the output A of the sense current amplifier LSV. Furthermore, at a reference current source terminal REF, a reference current source is connected to the current node connected to the output A. The reference current source according to the prior art is likewise connected to the supply voltage VDD and can be selected by means of a selection signal SS2. The summation current node has an intrinsic capacitance CA.
FIG. 3 shows the reference current source according to the prior art as illustrated in FIG. 2. The reference current source contains a plurality of N-MOSFET transistors T1, T2, and T3. The N-MOSFET transistor T1 of the reference current source generates a constant current in a manner dependent on the selection signal SS2. If the selection signal SS2 is logic 0, the constant current IK of the MOSFET transistor T1 is zero. Conversely, if the selection signal SS2 is switched on, a constant current IKxc3x8 with a specific constant current magnitude flows through the N-MOSFET transistor T1. The following hold true:
IK=0 if SS2=1
IK=IKxc3x8 if SS2=xc3x8xe2x80x83xe2x80x83(1)
The reference current source according to the prior art furthermore contains a current mirror circuit comprising the two N-MOSFET transistors T2 and T3, the two gate terminals of the two N-MOSFET transistors T2 and T3 being connected to one another and having a direct connection to the source terminal of the N-MOSFET transistor T1. The constant current IKxc3x8 is mirrored by the current mirror circuit T2 and T3, the current gain being determined by the current channel width/length ratio W/L of the two transistors T2 and T3.
The N-MOSFET T2 of the current mirror circuit has a source terminal connected to ground and a drain terminal connected to the reference current terminal REF. The current mirror circuit T2 and T3 generates a constant reference current IREFxc3x8 at the reference current terminal REF, the following holding true:                               I                      REF            ⁢                          xe2x80x83                        ⁢            ∅                          =                                            μ              ⁢                              xe2x80x83                            ⁢              Cox              ⁢                              xe2x80x83                            ⁢                              W                /                L                                      2                    ⁢                                    (                                                V                  GS                                -                                  V                  T                                            )                        2                                              (        2        )            
where:
W/L is the channel width/length ratio of the transistor T2,
Cox is the capacitance of the dielectric,
VT is the threshold voltage of the transistor T2, and
VGS is the gate/source voltage of the transistor T2.
Since the voltage VGS between the gate and the source of the transistor T2 is constant and the remaining quantities are also predetermined, the reference current IREFO generated by the reference current source is constant.
FIG. 4 shows the current mirror circuit contained in the sense current amplifier according to the prior art. The current mirror circuit contains two P-MOSFETs T4 and T5, whose gate terminals are connected to one another and are connected to the input E of the current mirror circuit. The two drain terminals of the two P-MOSFETS T4 and T5 are connected to the supply voltage potential VDD. The source terminal of the first P-MOSFET T4 is likewise connected to the signal input E of the current mirror circuit and receives the memory signal current IBL. The channel width/length ratios W/L of the two P-MOSFETs T4 and T5 are defined in such a way that the memory signal current IBL is output amplified by a fixed gain factor K at the source terminal of the second P-MOSFET T5.
In the conventional sense current amplifier, as illustrated in FIG. 2, the following holds true for the output voltage at the output A:
VA=VDD if K*IBLxe2x89xa7IREFxc3x8
VA=xc3x8 if K*IBL less than IREFxc3x8xe2x80x83xe2x80x83(3)
In the conventional sense current amplifier according to the prior art, as illustrated in FIG. 2, one disadvantage is that a high reading speed for the readout of the memory cell SZ and a low power consumption P of the sense current amplifier LSV cannot be achieved simultaneously. This will be explained below with reference to the signal profile illustrated in FIG. 5. If the memory cell SZ is not being read, the output A of the sense current amplifier LSV is at a predetermined high potential corresponding to the supply voltage VDD. If the memory cell SZ is not being read, the memory signal current IBL is 0.
At the instant t1, a read operation A is initiated in the example illustrated in FIG. 5, in the course of which a memory cell SZ which is in a logic low state L is read. When reading from a memory cell SZ which assumes a logic low state L, a memory signal current IBL of zero is generated, so that an output current of K*IBL which is lower than the constant reference current IREPxc3x8 flowing into the reference current source is also output at the output of the current mirror circuit. Since the reference current IREFO flowing from the current node is greater than the amplified memory signal current (K*IBL) flowing into the current node A, the intrinsic or parasitic capacitance CA at the output A of the sense current amplifier LSV according to the prior art is discharged, so that the output voltage VA at the output A of the sense current amplifier falls, as is illustrated in FIG. 5.
The discharge process at the output A of the sense current amplifier LSV takes place more quickly the higher the constant reference current IREFO. The discharge process lasts for a relatively long time in the case of a relatively low reference current IREFOA while the discharge process takes place quickly in the case of a relatively high reference current IREFC.
For the discharge time xcfx84 of the intrinsic capacitance CA at the output A of the sense current amplifier LSV according to the prior art, the following therefore holds true to an approximation:
xcfx84≅VDD/IREFxc3x8*CAxe2x80x83xe2x80x83(4)
The faster the discharge process takes place at the 5 output A of the sense current amplifier LSV, the higher the read-out speeds that can be achieved by means of the semiconductor memory.
At the instant t2, the read operation A is ended and the output node A of the sense current amplifier is charged again. At the instant t3, a further read operation B is initiated, in the course of which the memory cell SZ is this time read in a logic high state H. In this state, the memory cell SZ yields a memory signal current IBL of predetermined magnitude which is amplified by the current mirror circuit. Since the amplified signal current K*IBL is greater than the constant reference current IREFO, the output voltage VA at the output A of the sense current amplifier, in accordance with equation (3), is VA=VDD.
The following problem area exists in the case of the conventional sense current amplifier LSV, as illustrated in FIG. 2. The higher the constant reference current IREFO, the shorter the discharge time xcfx84 and the shorter the possible read-out times of the memory. However, this has the result that, in accordance with equation (3), the current gain K through the current mirror circuit must be high enough, when reading from a memory cell SZ which is in a logic high state, to satisfy the inequality condition and to switch reliably to the high voltage potential VDD at the output A. However, a high gain factor K of the current mirror circuit is equivalent to a high power loss P of the sense current amplifier LSV. The high power loss P entails a number of disadvantages. The higher the power loss P, the higher the temperature T generated by the sense current amplifier LSV, thus necessitating cooling devices, under certain circumstances. Furthermore, wider power supply lines become necessary in an integrated sense current amplifier LSV, in order to achieve the required power. A further disadvantage is that, in the case of battery-operated sense current amplifiers LSV, the batteries have to be recharged at shorter time intervals. This has considerable disadvantages in particular in the case of portable devices containing semiconductor memories, such as e.g. portable telephones.
Therefore, an object of the present invention is to provide a sense current amplifier which, on the one hand, enables a high speed when reading from a semiconductor memory and at the same time has a low power consumption.
The invention provides a high-speed sense current amplifier with a low power consumption for a memory cell, the sense current amplifier having: a first current mirror circuit, which amplifies a memory signal current received from the memory cell via a memory signal line and outputs it at a signal output of the sense current amplifier; a second current mirror circuit, which generates a setting current in a manner dependent on the received memory signal current; and an adjustable reference current source, which outputs a reference current to the signal output of the sense current amplifier, the magnitude of the output reference current being set, via a setting line, in a manner dependent on the setting current generated by the second current mirror circuit.
Preferred embodiments of the high-speed sense current amplifier according to the invention are described below with reference to the accompanying figures for elucidating features that are essential to the invention.